Packaging Solution for SiC Power Modules with a Fail-to-Short Capability

2021-08-11T16:55:16+02:00March 16th, 2019|Electronique de puissance & convertisseurs, Publications|

Fail-to-short packages, which can still carry current after the failure of their semiconductor devices, are required for HVDC applications. However, all existing solutions are dedicated to silicon components. Here, a fail-to-short package is proposed for SiC devices. Its manufacturing process is described. 4 modules are built and submitted to intense short circuit currents (up to 2000 A). It is found that they offer a stable short-circuit failure mode, providing that the modules are mechanically clamped to prevent separation during the surge current test.

FMEA of a non-selective fault-clearing strategy for HVDC grids

2021-08-11T16:55:33+02:00February 7th, 2019|Architecture & systèmes du supergrid, Publications|

The Failure Mode Effect Analysis (FMEA) is a technique used to investigate failures in a process or component and to identify the resultant effects of these failures on system operations. In this paper it is explained how the FMEA can be used to define and assess the impact of the failure modes (FM) of a protection strategy for High Voltage Direct Current (HVDC) grids.

Study of the impact of DC-DC converters on the protection strategy of HVDC grids

2021-08-11T16:55:54+02:00February 7th, 2019|Electronique de puissance & convertisseurs, Publications|

This paper studies the role of DC-DC converters in the protection of HVDC grids acting as firewalls to stop the propagation of faults. The effects of blocking the converter or actively controlling its operation during faults are presented.The results demonstrate the capabilities of DC-DC converters beyond DC voltage transformation.

25 kV-50 Hz railway power supply system emulation for Power-Hardware-in-the-Loop testings

2021-08-11T16:56:14+02:00January 8th, 2019|Electronique de puissance & convertisseurs, Publications|

This paper presents a methodology to consider the impedance of a grid in power hardware in the loop (PHIL) experiments to validate power converter control in presence of harmonics or resonances in the network impedance. As the phenomena to emulate are in a large frequency range, the skin effect in conductors has to be taken into account. A procedure is developed to model the network.

Modelling of a 25 kV-50 Hz railway infrastructure for harmonic analysis

2021-08-11T16:56:29+02:00December 20th, 2018|Electronique de puissance & convertisseurs, Publications|

This paper presents a methodology for the modelling of a 25 kV-50 Hz railway infrastructure, for frequencies from 0 to 5 kHz. It aims to quantify the amplifications of current and voltage harmonics generated by on-board converters into the infrastructure. A circuit is developed to model the skin effect in the overhead line for time-domain simulations. A new approach, based on state space representation and transfer functions, is also proposed to analyse the interactions between trains.

Design of a 1200 V, 100 kW Power Converter: How Good are the Design and Modelling Tools?

2021-08-11T16:56:54+02:00November 21st, 2018|Electronique de puissance & convertisseurs, Publications|

During the design of power converter, design mistakes must be avoided, especially for high voltage and high power converters. Simulation tools can be used to help the designers and limit the risks. This presentation will present a design flow approach used to design and validate a 1.2 kV – 100 kW DC-DC converter which was design from die to converter levels and started for a “blank page”. The presentation is organized in four parts. Firstly, the context of the work is introduced. Then, the simulation flow approach used to validate the design is presented. For this part, the presentation will focus on the system level simulation of one inverter, including the power modules. This part will highlight the main limitations of the current simulation tools found by the designers. In the third part, an enhanced approach is proposed to overcome the limitations and the first results are presented Finally, a conclusion will be presented.

Study of Turn-to-Turn Electrical Breakdown for Superconducting Fault Current Limiter Applications

2021-08-11T16:57:02+02:00November 2nd, 2018|Appareillage électrique haute tension, Publications|

The rational insulation design of a resistive superconducting fault current limiter (r-SCFCL) requires data gathered from experimental setups representative of the final apparatus. Therefore, an experimental study was performed to characterize the electrical breakdown (BD) of liquid nitrogen (LN2) in the peculiar conditions of a quenching superconducting device.

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