APEC 2017 “Robustness of SiC MOSFET under Avalanche Conditions”
APEC 2017 “Robustness of SiC MOSFET under Avalanche Conditions”
Robustness of SiC MOSFET under Avalanche Conditions
Abstract
In high voltage direct current (HVDC) converters, a series connection of semiconductor devices is often used to achieve the desired blocking voltage. In such configuration, an unequal voltage sharing may drive one or more devices into avalanche breakdown, eventually causing the failure of the entire group of devices. This paper presents the experimental evaluation of SiC MOSFETs from different manufacturers operated in avalanche. A setup was developed to test the devices under such condition. The reliability of SiC MOSFETs have been compared.
To correlate the experimental results with the failure mechanism, the MOSFETs were decapsulated to identify the failure sites on the SiC dies. Examination results show that for some tested devices, the failure occurs at the metallization source of the die, and results in a short circuit between all three terminals of the MOSFETs.
Furthermore, it has been found that the parasitic BJT latch up and the intrinsic temperature limit are the main failure mechanisms for these devices.
To correlate the experimental results with the failure mechanism, the MOSFETs were decapsulated to identify the failure sites on the SiC dies. Examination results show that for some tested devices, the failure occurs at the metallization source of the die, and results in a short circuit between all three terminals of the MOSFETs.
Furthermore, it has been found that the parasitic BJT latch up and the intrinsic temperature limit are the main failure mechanisms for these devices.
Dchar I.1, Zolkos M.1, Buttay C.2 & Morel H.2
1 SuperGrid Institute, Villeurbanne, France
2 Univ Lyon, CNRS, INSA-Lyon, Laboratoire Ampère, UMR 5005, Villeurbanne, France
APEC ’17 Tampa, USA
26-30th Mars 2017
Keywords: Reliability, SiC MOSFET, Avalanche breakdown, Failure mechanism, Critical energy, Parasitic BJT